Jiayun Cheng

I'm Cheng Jiayun, a recent graduate from the University of Technology Malaysia (UTM). I'm passionate about Analog CMOS design and VLSI. With a strong foundation in these fields, I'm excited to apply my skills and contribute to the semiconductor industry. I'm eager to embrace new challenges, collaborate with professionals, and make a meaningful impact in integrated circuit design.

• Intern at Intel Malaysia for 3 months.
• IC Design Engineer with experience in the complete IC design flow.
• Attended the Elite program to gain comprehensive knowledge in IC design.
• Proficient in using Perl scripting for text extraction and implementing Engineering Change Orders (ECO) to enhance the design.

• University of Technology Malaysia (UTM)
• Bachelor Degree of Electronic Engineering
• Major in IC design (Electronic System Design)