Lead Engineer, Hardware Design - Penang, Malaysia - Celestica Electronics (S) Pte Ltd

Description

General Overview

Functional Area: Engineering
Career Stream: Design Engineering Hardware
SAP Short Name: LEN-ENG-DHW
Job Level: Level 08
IC/MGR: Individual Contributor
Direct/Indirect Indicator: Indirect

Summary

The Signal and Power Integrity Engineer will play a critical role in the planning of digital PCB designs, simulation, lab verification, and troubleshooting signal integrity issues on completed designs. They will also be expected to help with design review of critical PCBs for signal integrity concerns. Good communications skills and ability to work with global teams is required.

The incumbent develops new electrical systems/circuits for various applications. Research system ideas and draw up plans for these systems, and capture them in schematics and system specifications. Test, simulate, validate and qualify their systems and make adjustments as needed. Provide support throughout the manufacturing of the electrical systems they have designed.

This role works in cross functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations.

Detailed Description

Develop SI and PI design for server/storage/communication products. Major works are to serve as the signal and power integrity analyst and designer provides the support to internal team, suppliers, and customers to deliver the new products.

• PCB material choosing and stack-up definition.
• 3D passive channel modeling, perform extraction by using electromagnetic tools.
• Perform signal integrity pre-layout and post-layout analysis in R&D phase.
• Perform static timing and signal integrity analysis of parallel (common clock, source- . synchronous) interfaces.
• Design and analysis of multi-gigabit serial links, including lab verification and tuning.
• Perform power integrity analysis on power delivery network.
• Generate and verify PCB layout rules, manage constraints for PCB layout.
• Work directly with ASIC and PCB design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability.
• Cooperate with R&D team and signal test engineers on debugging, failure analysis and fixing issues discovered during test.
• Familiar with SAS, PCIe, DDR3/4, 25G/56G Ethernet specification is a plus.

Knowledge/Skills/Competencies

• Experience with at least one PCB post-route SI tool: Cadence SPECCTRAQuest, Mentor ICX, SiSoft SI-Auditor (preferred), Sigrity Power SI.
• Experience with Synopsys HSPICE and/or Keysight ADS for both time and frequency domain circuit simulation.
• Experience with at least one 3-D field solver (CST Microwave Studio, ANSYS HFSS).
• Experience with TDR and VNA measurements.
• Proficiency in Electromagnetic, Transmission-line & S-parameters theory and modeling.
• Good understanding on power distribution, DDR and SerDes design.
• BSEE or related field with 5 years of applicable work experience or MSEE or related field with 3 years of experience.
• Experience of script languages like VB, Perl or Python.
• Use of mathematic tools like Matlab.
• Strong written and oral communication in English with customer service skills

Physical Demands

• Duties of this position are performed in a normal office environment.
• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
• Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
• Occasional travel may be required.

Typical Experience

• 1 to 3 years of related experiencExperience in similar job roles

Typical Education

• Bachelor's Degree

Notes

This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.