Iylia Adhwa

Working on designing using base metal layer until highest metal layer from scratch using cadence and genesis tools. Performing all aspect of the SoC design flow from high level design to synthesis, place, and route as a back-end process. Perform placement and routing, LVS (layout versus schematic) verification, DRCD verification, and density check. Had been working on creating/modify standard cell (full custom design) library, metal routing, and analog design. Having an experience with various undergoing and latest project on 7nm and 22nm. Able to grab the opportunity by gaining trust to lead and pioneering one of the projects in intel.

Working on designing using base metal layer until highest metal layer from scratch using cadence and genesis tools. Performing all aspect of the SoC design flow from high level design to synthesis, place, and route as a back-end process. Perform placement and routing, LVS (layout versus schematic) verification, DRCD verification, and density check. Had been working on creating/modify standard cell (full custom design) library, metal routing, and analog design. Having an experience with various undergoing and latest project on 7nm and 22nm. Able to grab the opportunity by gaining trust to lead and pioneering one of the projects in intel.

I pursuing my master's in Electrical Engineering which focuses on AI systems that use image processing and deep learning to assess the quality of fruit. In my diploma and degree, I major in electronic engineering which exposed me to IC design tools and knowledge.